1. Field of the Invention
The present invention relates to a semiconductor device and a testing method for a semiconductor device. In particular, the invention relates to a semiconductor device and a testing method for a semiconductor device, both of which are used for testing two consecutive states.
2. Description of Related Art
Along with a recent tendency toward high-speed processors, memories have required high-speed processing as well as a large capacity. According as the memories have achieved high performance, a variety of tests are required for the memories. To that end, attentions have been paid to the way to test the memories.
What are necessary for testing the memories are the test accuracy high enough to reliably confirm a normal operation, and the lowest possible cost of the test.
In order to enhance the test accuracy, it is necessary to execute the test under the environments as similar to the actual operational environments as possible. Thus, an operational clock for testing the memory is desirably similar to the actual operational clock. In most cases, however, the test is executed at low clock frequencies in consideration of cyclic redundancy check.
As a measure therefor, there has been proposed a testing method that enables the high-speed test by means of an internal delay circuit or the like, even if the low clock frequencies can only be externally applied (see Japanese Unexamined Patent Publication No. 2002-230999, for instance).
The related art is described hereinbelow. FIG. 8 shows a configuration example and timing example of a semiconductor device of the related art. The device shown in FIG. 8 is connected with an evaluating tester, and provided with a clock/address controller circuit, a function controller circuit, a data controller circuit, and a RAM macro operable at high speeds.
The clock/address controller circuit receives two kinds of external clock, CLKA and CLKB from the evaluating tester to generate TCLK based on CLKA and CLKB to be sent to the RAM macro. Here, two-phase clock signals, CLKA and CLKB are unnecessary except when the memory is tested. A clock signal corresponding to TCLK may be directly generated and supplied to the RAM macro in the actual operation. The RAM macro runs based on TCLK output from the clock/address controller circuit. Further, the clock/address controller circuit also receives an external address to access the corresponding address of the RAM macro.
The function controller circuit receives control signals for reading, writing, and refreshing from the evaluating tester to control the RAM macro in accordance with the received control signals. The data controller circuit receives data to be written from the evaluating tester to write this data to the RAM macro. Besides, the data controller circuit receives data read from the RAM macro to output this data to the evaluating tester.
The timing charts of the input of the external address (ADD), the access to the RAM macro in accordance with the address (INT_ADD), and the data output from the RAM macro (TQ) are shown in FIG. 8. As regards the access to the RAM macro, the bit line is precharged during the time of tRP of FIG. 8. During the time of tRAS, the voltage level of the word line is raised to write/read data to/from a corresponding memory cell. That is, in order to shorten tRP, a time period from the rising edge of CLKB to the falling edge of CLKA have to be reduced.
According to the method of the related art, however, either the precharge, or the read/write access can be executed at high speeds, so both of them cannot be carried out at high speeds. This results in a problem that an operation failure that would occur only when both of them are carried out at high speeds cannot be detected. In addition, although Japanese Unexamined Patent Publication No. 2002-230999 describes the method of testing a high-speed RAM using a low-speed tester, this related art can only execute either the precharge or the read/write access at high speeds and cannot execute both of them at high speeds like the related art of FIG. 8.
As mentioned above, the conventional memory testing method has a problem that provided the low clock frequencies are applied, the read/write test for the memory that would be carried out during the precharge and read/write access processings cannot be concurrently executed during both of the precharge processing and read/write access processing at much higher actual operational clock frequencies.